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W83C43 keyboard controller publication release date: january 1996 - 1 - revision a2 general description the W83C43 is a keyboard controller designed to provide the functions needed to interface a cpu to a keyboard or to a ps/2 mouse. the W83C43 can be used with ibm - compatible personal computers or ps/2 - based systems. the controller recei ves serial data from the keyboard or ps/2 mouse, checks the parity of the data, and presents the data to the system as a byte of data in its output buffer. the controller will interrupt the system when data are placed in its output buffer. the keyboard and ps/2 mouse are required to acknowledge all data transmissions. no transmission should be sent to the keyboard or ps/2 mouse until acknowledge is received for the previous byte sent. this fast keyboard controller can improve the performance of ibm pc/at 3 86 ? dx/sx and 486 ? dx/sx machines and their compatibles. hardwire methodology is used in this controller instead of software implementation, as in the traditional 8042 keyboard bios. with full hardware implementation, this enables the keyboard controller to respond instantly to all commands sent from the keyboard and ps/2 mouse to the cpu bios. the keyboard controller enables popular programs such as autocad , microsoft windows ? 3.1, novell , and other programs to run much faster. features supports ibm pc/at 386 dx/sx and 486 dx/sx system designs full hardwire design based on advanced vlsi cmos technology supports ps/2 mouse 6 mhz to 12 mhz operating frequency supports at mode and ps/2 mode for different hardware configurations automatically detects ps/2 mode or at mode much faster than traditional keyboard controller packaged in 40 - pin dip or 44 - pin plcc
W83C43 - 2 - pin configurations vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 39 40 34 35 36 37 38 30 31 32 33 26 27 28 29 21 22 23 24 25 t1 p27 (kdat) p26 (kclk) p25 (iemp/mint) p24 (kint) p17 (kinh) p16 (disp) p15 (jump) p14 (ram) p13 p12 nc p10 p11 p20 (rc) p21 (ga20) p22 (nc/mdat) p23 (nc/mclk) vcc t0 40-pin dip x2 reset vcc cs gnd wr nc rd a2 d0 gnd x1 44-pin plcc 40 2 1 44 43 42 41 6 5 4 3 39 38 37 36 35 34 33 32 31 30 29 p24 p17 p16 p15 p14 nc p13 p12 p11 p10 nc 28 27 26 25 24 23 22 21 20 19 18 17 10 9 8 7 14 13 12 11 16 15 cs gnd rd a2 wr nc nc d0 d1 d2 d3 p 2 5 d 7 g n d v c c n c p 2 3 p 2 2 p 2 1 p 2 0 d 6 d 5 d 4 d1 d2 d3 d4 d5 d6 d7 p 2 6 p 2 7 t 1 v c c n c t 0 x 1 x 2 / r e s e t v c c
W83C43 publication release date: january 1996 - 3 - revision a2 pin description pin no. i/o name function (40 - pin dip) (44 - pin plcc) at mode ps/2 mode 1 2 i t0 k/b clock input k/b clock input 2 3 i x1 crystal clock i/p crystal clock i/p 3 4 i x2 crystal clock i/p crystal clock i/p 4 5 i reset chip reset chip reset 5 6 - v cc optional +5v power supply optional + 5v power supply 6 7 i cs chip select chip select 7 8 - gn d optional ground power optional ground power 8 9 i rd i/o read i/o read 9 10 i a2 connect to address a2 connect to address a2 10 11 i wr i/o write i/o write 11, 26 1, 12, 13, 23, 29, 34 - nc reserved reserved 12, 13, 14, 15, 16, 17, 18, 19 14, 15, 16, 17, 18, 19, 20, 21 i/o d0 - d7 data bus d0 - d7 data bus d0 - d7 20 22 - gnd ground power supply ground power supply 21 24 o p20 bit 0 of port2 ( rc : system reset) bit 0 of port2 ( rc : sys tem reset) 22 25 o p21 bit 1 of port2 ( ga20 : gate a20) bit 1 of port2 ( ga20 : gate a20) 23 26 i/o p22 bit 2 of port2 (nc: user - defined i/o) bit 2 of port2 (mdat: mouse data output) 24 27 i/o p23 bit 3 of port2 (nc: user - defined i/o) bit 3 of port2 (mclk: mouse clock output) 25 28 - v cc optional +5v power supply optional + 5v power supply
W83C43 - 4 - pin description, continued pin no. i/o name function (40 - pin dip) (44 - pin plcc) at mode ps/2 mode 27 30 i/o pu* p10 bit 0 of port1 (user - defined i/o) bit 0 of port1 (k/b data input) 28 31 i/o pu* p11 bit 1 of port1 (user - defined i/o) bit 1 of port1 (mouse data input) 29 32 i/o p12 bit 2 of port2 (user - defined i/o) bit 2 of port2 (user - defined i/o) 30 33 i/o p13 bit 3 of port1 (user - defined i/o) bit 3 of port1 (user - defined i/o) 31 35 i pu* p14 bit 4 of port1 (ram: ram jumper select) bit 4 of port1 (ram: ram jumper select) 32 36 i pu* p15 bit 5 of port1 (jump: jumper) bit 5 of port1 (jump: jumper) 33 37 i pu* p16 bit 6 of port 1 (disp: display select) bit 6 of port1 (disp: display select) 34 38 i pu* p17 bit 7 of port1 (kinh: k/b inhibit switch) bit 7 of port1 (kinh: k/b inhibit switch) 35 39 o p24 bit 4 of port2 (kint: k/b obf o/p interrupt) bit 4 of port2 (kint: k/b obf o/p interrupt) 36 40 o p25 bit 5 of port2 (iemp: i/p buffer empty) bit 5 of port2 (mint: mouse obf o/p interrupt) 37 41 o p26 bit 6 of port2 (kclk: k/b clock output) bit 6 of port2 (kclk: k/b clock output) 38 42 o p27 bit 7 of port2 (kdat: k/b data output) bit 7 of port2 (kdat: k/b data output) 39 43 i t1 k/b data input mouse clock input 40 44 - vcc +5v power supply +5v power supply * internal pull - up resistor
W83C43 publication release date: january 1996 - 5 - revision a2 block diagram scan code rom receive control hardwire control & select logic status buffer register r64 w60 w64 r60 input buffer register buffer register output data buffer register d0~d7 t0 t1 wr rd cs a2 reset transmit contrrol register status transmit register input & output port interface output port interface p20 (rc) p21 (ga20) p22 (nc/mdat) p23 (nc/mclk) p24 (kint) p25 (iemp/mint) p26 (kclk) p27 (kdat) p10 p11 p12 p13 p14 (ram) p15 (jump) p16 (disp) p17 (kinh) x2 x1 absolute maximum rat ings parameter rating unit ambient operating temperature - 0 to + 85 c storage temperature - 65 to + 150 c supply voltage to ground potential - 0.3 to + 7.0 v applied input/output voltage - 0.3 to + 7.0 v power dissipation 50 mw note: exposure to conditions beyond those li sted under absolute maximum ratings may adversely affect the life and reliability of the device.
W83C43 - 6 - electrical character istics & capacitance (ta = 0 c to + 70 c, v dd = +5v 5%) symbol description min. typ. max. unit note v dd power supply 4.75 5.0 5.25 v v il input low voltage (except reset, t0, t1) 0.8 v v il1 input low voltage (reset, t0, t1) 0.6 v v ih1 input high voltage (except reset, t0, t1, p10, p11) 2.0 v v ih2 input high voltage (p10, p11) 3.0 v v ih3 input high voltage (t0, t1, rese t) 3.5 v v oh1 output high voltage (p10 - p13, p20 - p27) 2.4 v i oh = - 2 ma v oh2 output high voltage (d0 - d7) 2.4 v i oh = - 4 ma v ol 1 output low voltage (p10 - p13, p20 - p27) 0.4 v i ol = 2 ma v ol 2 output low voltage (d0 - d7) 0.4 v i ol = 4 ma r ip min. i/p resist 10k w i ofl o/p leakage current (d0 - d7, high z state) - 10 10 m a i ih i/p leakage current - 10 10 m a v dd = 5.5v, v in = v dd i il i/p leakage current (except p10, p11, p14, p15, p16, p17) - 10 10 m a v dd = 5.5v, v in = v ss i il1 i/p leakage current (p10, p11, p14, p15, p16, p17) - 10 550 m a v dd = 5.5v, v in = v ss c l o/p load capacity 15 50 pf status register (at mode) the status register is an 8 - bit read - only register at i/o address hex 64 that holds information about the status of the keyboard controller and interface. it may be read at any time. bit bit function description 0 output buffer full 0: output buffer empty 1: output buffer full 1 input buffer full 0: input buffer empty 1: input buffer full
W83C43 publication release date: january 1996 - 7 - revision a2 status register (at mode), cont inued bit bit function description 2 system flag this bit may be set to 0 or 1 by writing to the system flag bit in the command byte of the keyboard controller. it is set to 0 after a power - on reset 3 command/data 0: data byte 1: command byte 4 inhibit switch 0: keyboard is inhibited 1: keyboard is not inhibited 5 transmit time - out 0: no transmit time - out error 1: transmit time - out error 6 receive time - out 0: no receive time - out error 1: receive time - out error 7 parity error 0: odd parity (no error) 1 : even parity (error) output buffer the output buffer is an 8 - bit read - only register at i/o address hex 60. the keyboard controller uses the output buffer to send the scan code received from the keyboard and data bytes required by commands to the system. the output buffer should be read only when the output buffer full bit in the register is 1. onput buffer the input buffer is an 8 - bit write - only register at i/o address hex 60 or 64. writing to address hex 60 sets a flag that indicates a data write; writin g to address hex 64 sets a flag that indicates a command write. data written to i/o address hex 60 are sent to the keyboard (unless the keyboard controller is expecting a data byte) following the controller's input buffer only if the input buffer full bit in the status register is set to 0. (a) input port definition (at mode) bit function 0 undefined 1 undefined 2 undefined 3 undefined 4 ram on system board 0: disable second 256 kb of system board ram 1: enable second 256 kb of system board ram
W83C43 - 8 - (a) input port definition (at mode), continued bit function 5 manufacturing jumper installed 0: manufacturing jumper 1: jumper not installed 6 display type switch 0: primary display attached to color/graphics 1: primary display attached to monochrome 7 keyboard inhibit switch 0: keyboard inhibited 1: keyboard not inhibited (b) output port definition (at mode) bit function 0 system reset 1 gate a20 2 undefined 3 undefined 4 output buffer full 5 input buffer empty 6 keyboard clock (output) 7 keyboard data (output) (c) test - input port definition (at mode) bit function 0 keyboard clock (input) 1 keyboard data (input) status register (ps/2 mode) bit bit function description 0 output buffer full 0: output buffer empty 1: output buffer full 1 input buffer full 0: input buffer empty 1: input buffer full 2 system flag this bit may be set to 0 or 1 by writting to the system flag bit in the command byte of the keyboard controller. it is set to 0 after a power - on reset.
W83C43 publication release date: january 1996 - 9 - revision a2 status register (ps/2 mode), cont inued bit bit function description 3 command/data 0: data byte 1: command byte 4 inhinit switch 0: keyboard is inhibited 1: keyboard is not inhibited 5 auxiliary device output buffer 0: auxiliary device output buffer empty 1: auxiliary device output buffer full 6 general purpose time - out 0: no time - out error 1: time - out error 7 parity error 0: odd parity 1: even parity (error) input port definition bit function 0 keyboard data input 1 mouse data input 2 undefined 3 undefined 4 ram on system board 0: disable second 256 kb of system board ram 1: enable second 256 kb of system board ram 5 manufacturing jumper 0: manufacturing jumper 1: jumper not installed 6 display type switch 0: primary display attached to color/graphics 1: primary display attached to monochrome 7 keyboard input switch 0: keyboard inhibited 1: keyboard not inhibited output port definition bit function 0 system reset 1 gate a20 2 mouse data output 3 mouse clock output
W83C43 - 10 - output port definition, continued bit function 4 keyboa rd output buffer full interrupt 5 mouse output buffer full interrupt 6 keyboard clock output 7 keyboard data output test - input port definition bit function 0 keyboard clock input 1 mouse clock input commands (i/o address hex 64) (at mode) command function 20 read command byte of keyboard controller 60 write command byte of keyboard controller bit 1 2 3 4 5 6 7 0 bit definition reserved ibm pc compatible mode ibm pc mode disable keyboard inhibit override system flag reserved enable output buffer full interrupt aa self - test ab interface test bit 04 03 02 01 00 bit definition no error detected k/b clock line is stuck low k/b clock line is stuck high k/b data line is stuck low k/b data line is stuck high ad disable keyboard feature ae enable keyboard interface
W83C43 publication release date: january 1996 - 11 - revision a2 commands ( i/o address hex 64) (at mode), continued command function c0 read input port d0 read output port d1 write output port e0 read test inputs f0 - ff pulse output port commands (i/o address hex 64) (ps/2 mode) command function 20 read command byte of keyboard controller 60 write command byte of keyboard controller bit 1 2 3 4 5 6 7 0 bit definition reserved ibm keyboard translate mode disable auxiliary device disable keyboard reserve system flag enable auxiliary interrupt enable keyboard interrupt a7 disable auxiliary device interface a8 enable auxiliary device interface a9 interface test bit 04 03 02 01 00 bit definition no error detected auxiliary device "clock" line is stuck low auxiliary device "clock" line is stuck high auxiliary device "data" line is stuck low auxiliary device "data" line is stuck low aa self - test
W83C43 - 12 - commands (i/o address hex 64) (ps/2 mode), continued command function ab interface test bit 04 03 02 01 00 bit definition no error detected keyboard "clock" line is stuck low keyboard "clock" line is stuck high keyboard "data" line is stuck low keyboard "data" line is stuck high ad disable keyboard interface ae enable keyboard interface c0 read input port c1 poll input port low c2 poll input port high d0 read output port d1 write output port d2 write keyboard output buffer d3 write auxiliary device output buffer d4 write to auxiliary device e0 read test inputs f0 - ff pulse output port ac timing no. description min. max. unit t1 address setup time from wrb 0 ns t2 address setup time from rdb 0 ns t3 wrb strobe width 20 ns t4 rdb strobe width 20 ns t5 address hold time from wrb 0 ns t6 address hold time from rdb 0 ns t7 data setup time 50 ns t8 data hold time 0 ns t9 gate delay time from wrb 10 30 ns
W83C43 publication release date: january 1996 - 13 - revision a2 ac timing, continued no. description min. max. unit t10 rdb to drive data delay 40 ns t11 rdb to floating data delay 0 20 ns t12 data valid after clock falling (send) 4 m s t13 k/b clock period 20 m s t14 k/b clock pulse width 10 m s t15 d ata valid before clock falling (receive) 4 m s t16 k/b ack after finish receiving 20 m s t17 rc fast reset pulse delay (8 mhz) 2 3 m s t18 rc pulse width (8 mhz) 6 m s t19 transmit timeout 2 ms t20 data valid hold time 0 m s t21 x1/x2 period (6 - 12 mhz) 83 167 ns t22 duration of clk inactive 30 50 m s t23 duration of clk active 30 50 m s t24 time from inactive clk transition, used to time when the auxiliary device sample data 5 25 m s t25 time of inhibit mode 100 300 m s t26 time from rising edge of clk to data transition 5 t28 - 5 m s t27 duration of clk inactive 30 50 m s t28 duration of clk active 30 50 m s t29 time from data transition to falling edge of clk 5 25 m s t30 mode detect signal after p10 goes high typical 1 ms t31 high pulse of mode detect signal typical 220 m s t32 low pulse of mode detect signal typical 220 m s t33 mode detect signal after reset goes high typical 1 ms t34 time out of at mode? s mode detect signal typical 64 ms
W83C43 - 14 - timing waveforms write cycle timing t1 t3 t7 t8 t9 t17 t18 active data in a2, csb wrb d0~d7 ga20 output port fast reset pulse rc fe command t5 read cycle timing data out active t2 t4 t6 t10 t11 a2,csb aen rdb d0-d7 send data to k/b clock (kclk) serial data (kdat) d0 d1 d2 d3 d4 d5 d6 d7 p stop start t12 t14 t13 t16 t19
W83C43 publication release date: january 1996 - 15 - revision a2 receive data from k/b clock (kclk) serial data (t1) t15 t14 t13 t20 d0 d1 d2 d3 d4 d5 d6 d7 p stop start x1/x2 clock t21 clock clock send data to mouse mclk mdat t25 t22 t23 t24 d0 d1 d2 d3 d4 d5 d6 d7 p stop bit start bit receive data from mouse t29 t26 t27 mclk t28 mdat d0 d1 d2 d3 d4 d5 d6 d7 p stop bit start
W83C43 - 16 - ps2 mode's mode detect (p10 released to high by keyboard before reset goes high) reset p27 p10 t31 t32 t33 ps2 mode's mode detect (p10 released to high by key board after reset goes high) reset p27 p10 t31 t32 t30 at mode's mode detect (p10 internal pull high. as there is no external loop between p27 and p10 so p27 issues pulse until time out ) reset p27 p10 t31 t33 t32 t34
W83C43 publication release date: january 1996 - 17 - revision a2 typical application circuits application for at mode x1 2 x2 3 reset 4 t0 1 t1 39 a2 9 cs 6 vcc 5 rd 8 wr 10 d0 12 d1 13 d2 14 d3 15 d4 16 d5 17 d6 18 d7 19 gnd 7 gnd 20 vcc 40 vcc 25 p10 27 p11 28 p12 29 p13 30 p14 31 p15 32 p16 33 p17 34 p20 21 p21 22 p22 23 p23 24 p24/ob 35 p25 36 p26/kclk 37 p27/kdat 38 nc 11 nc 26 kb8042-dip ram select jumper manufacturing mode jumper rcb gate20 resetb sa2 8042cs# iord# iowr# d[0..7] 1 2 74als04 keyboard interrupt vcc 1 2 7407 keyboard clock keyboard data 1 2 7407
W83C43 - 18 - application for ps/2 mode keyboard interrupt x1 2 x2 3 reset 4 t0 1 t1 39 a2 9 cs 6 vcc 5 rd 8 wr 10 d0 12 d1 13 d2 14 d3 15 d4 16 d5 17 d6 18 d7 19 gnd 7 gnd 20 vcc 40 vcc 25 p10 27 p11 28 p12 29 p13 30 p14 31 p15 32 p16 33 p17 34 p20 21 p21 22 p22 23 p23 24 p24/ob 35 p25 36 p26/kclk 37 p27/kdat 38 nc 11 nc 26 kb8042-dip ps/2 mouse interrupt ram select jumper manufacturing mode jumper rcb gate20 resetb sa2 8042cs# iord# iowr# d[0..7] 1 2 7406 vcc ps/2 mouse data vcc ps/2 mouse clock 1 2 7406 1 2 7406 1 2 7406 keyboard clock keyboard data
W83C43 publication release date: january 1996 - 19 - revision a2 driving from external source option 2 pclk x1 1 2 2 x2 3 n.c. option 1 2 x1 3 x2 1 2 pclk option 3 +5v 470 470 pclk 1 2 7404 1 2 7407 2 x1 x2 3 1 2 7407
W83C43 - 20 - package dimensions 40 - pin dip 1. dimensions d max & s include mold flash or tie bar burrs. 2. dimension e1 does not include interlead flash. 3. dimensions d & e1 include mold mismatch and are determined at the mold parting line. 6. general appearance spec. should be based on final visual inspection spec. . 1.37 1.22 0.054 0.048 notes: symbol min. nom. max. max. nom. min. dimension in inch dimension in mm a b c d e a l s a a 1 2 e 0.050 1.27 0.210 5.33 0.010 0.150 0.016 0.155 0.018 0.160 0.022 3.81 0.41 0.25 3.94 0.46 4.06 0.56 0.008 0.120 0.670 0.010 0.130 0.014 0.140 0.20 3.05 0.25 3.30 0.36 3.56 0.540 0.550 0.545 13.72 13.97 13.84 17.02 15.24 14.99 15.49 0.600 0.590 0.610 2.29 2.54 2.79 0.090 0.100 0.110 b 1 1 e e 1 a 2.055 2.070 52.20 52.58 0 15 0.090 2.29 0.650 0.630 16.00 16.51 protrusion/intrusion. 4. dimension b1 does not include dambar 5. controlling dimension: inches. 15 0 seating plane e a 2 a a c e base plane 1 a 1 e l a s 1 e d 1 b b 40 21 20 1 44 - pin plcc 44 40 39 29 28 18 17 7 6 1 l c 1 b 2 a h d d e b e h e y a a 1 seating plane d g g e notes: symbol min. nom. max. max. nom. min. dimension in inch dimension in mm a b c d e h e l y a a 1 2 e b 1 h d g g d e on final visual inspection spec. 4. general appearance spec. should be based 3. controlling dimension: inches protrusion/intrusion 2. dimension b1 does not include dambar flash. 1. dimensions d & e do not include interlead 0.020 0.145 0.026 0.016 0.008 0.648 0.590 0.680 0.090 0.150 0.028 0.018 0.010 0.653 0.610 0.690 0.100 0.050 bsc 0.185 0.155 0.032 0.022 0.014 0.658 0.630 0.700 0.110 0.004 0.51 3.68 0.66 0.41 0.20 16.46 14.99 17.27 2.29 3.81 0.71 0.46 0.25 16.59 15.49 17.53 2.54 1.27 4.70 3.94 0.81 0.56 0.36 16.71 16.00 17.78 2.79 0.10 bsc 16.71 16.59 16.46 0.658 0.653 0.648 16.00 15.49 14.99 0.630 0.610 0.590 17.78 17.53 17.27 0.700 0.690 0.680
W83C43 publication release date: january 1996 - 21 - revision a2 headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5792646 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-7197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-7190505 fax: 886-2-7197502 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii, 123 hoi bun rd., kwun tong, kowloon, hong kong tel: 852-27516023 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2730 orchard parkway, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-9436668 note: all data and specifications are subject to change without notice.

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